Manufacturing method of semiconductor device

ABSTRACT

It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 μg/m3 and less.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/147,591, filed May 5, 2016, which claims the benefit of JapanesePatent Application No. 2015-118656 filed on Jun. 11, 2015 including thespecification, drawings and abstract is incorporated herein by referencein its entirety.

BACKGROUND

The invention relates to a manufacturing method of a semiconductordevice and particularly, to a technique effectively applied to amanufacturing method of a semiconductor device using a sealed typetransfer container for carrying a semiconductor wafer.

For example, in a semiconductor device manufacturing method, using asemiconductor wafer having a diameter of 300 mm, a plurality ofsemiconductor wafers are pun in the sealed type transfer containercalled Front Open Unified Pod (FOUP) and carried among the processors.

Japanese Unexamined Patent Application Publication No. 2008-24429(Patent Document 1) shows that when a PSZ film is used to embed anelement isolation insulating film, a deformation of a pattern occurs inthe next photolithography process, hence to degrade the performance ofthe photolithography process. In other words, Si—N bond included in thePSZ film is hydrolyzed with water in the environment, to generate NH₃,and a high sensibility photoresist of chemical amplification typephotoresist used in the photolithography process reacts with basiccompound including nitrogen atoms such as NH₃ or amine, hence togenerate a pattern deformation. In the Japanese Unexamined PatentApplication Publication No. 2008-24429, an inactive gas is introducedinto a sealed type transfer container carried among the processes withsemiconductor wafers accommodated therein, to reduce the humidity insidethe sealed type transfer container more than the humidity of theenvironment such as a clean room, thereby avoiding the above-mentionedpattern deformation.

The paragraph [0118] of International Patent Laid-Open No. 2010-125682(Patent Document 2) discloses that a barrier insulating film BI1 isformed in a stacked structure of an SiCN film and an SiCO film in orderto avoid resist poisoning. In other words, by applying an ammonia plasmatreatment on the surface of an interlayer insulating film IL1 nitrogenexisting on the surface of the interlayer insulating film IL1 andnitrogen included in the SiCN film are chemically reacted together togenerate amine, which is diffused to the interlayer insulating film IL2on the barrier insulating film BI1. Then, the chemical amplificationtype resist used for forming a wiring groove in the interlayerinsulating film IL2 reacts with the amine, to generate a pattern failurein a photoresist film FR2; however, by providing the SiCO film betweenthe SiCN film and the interlayer insulating film IL2, the amine issuppressed from diffusing to the interlayer insulating film IL2, therebyavoiding the resist poisoning.

SUMMARY

Also, in a copper (Cu) wiring structure examined by the inventor et al.,similarly to the International Patent Laid-Open No. 2010-125682, abarrier insulating film having a stacked structure of an SiON film andan SiCO film is used. According to the examination by the inventor etal., even when using the barrier insulating film having the stackedstructure, it is found that a pattern failure of chemical amplificationtype resist called resist poisoning occurs also in the photolithographyprocess of forming a wiring groove in an interlayer insulating film onthe barrier insulating film.

According to the examination by the inventor et al., it is found thatthe above failure is caused by nitrogen or ammonium ion released fromthe silicon nitride film remaining on the rear surface of thesemiconductor wafer during the manufacturing process of the copper (Cu)wiring. When the silicon nitride film is deposited on the main surfaceof the semiconductor wafer, for example, in a batch typed Low PressureChemical Vapor Deposition (LPCVD) method, the silicon nitride film isalso deposited on the rear surface of the semiconductor wafer. In thecleaning step included in the manufacturing process of a semiconductordevice, the silicon nitride film formed on the rear surface is noteliminated but remains on the rear surface of the semiconductor wafer,and in this state as it remains, the manufacturing process of asemiconductor device is continued, to complete a semiconductor device.The silicon nitride film is removed in the rear surface polishingprocess of a semiconductor wafer for thinning the semiconductor wafer.Accordingly, for example, in the manufacturing process of a copperwiring, in a state where the silicon nitride film is formed on the rearsurface of the semiconductor wafer, the manufacturing process of thecopper wiring is performed. In some cases, a silicon oxide film isformed in the batch typed LPCVD method and the silicon oxide film isdeposited also on the rear surface of the semiconductor wafer; however,the silicon oxide film is removed in the above cleaning step.

In the manufacturing process of the copper wiring, a semiconductor waferis carried among the processes, being stored in the sealed type transfercontainer called FOUP. Since airtightness of the sealed type transfercontainer is high, for example, when the stored time gets longer becauseof a trouble of a device, the nitrogen or ammonium ion released from thesilicon nitride film remaining on the rear surface of the semiconductorwafer raises the nitrogen concentration or ammonium concentration(hereinafter, described as the ammonium concentration) within the sealedtype transfer container. A large amount of the ammonium ion is attachedto the main surface of the semiconductor wafer, and it is found that apattern failure of a chemical amplification type resist, called resistpoisoning, occurs in the photolithography process using the chemicalamplification type resist. The ammonium ion attached to the main surfaceof the semiconductor wafer generates amine and disturbs acid generationin the ultraviolet ray exposure portion of the positive chemicalamplification type resist, hence to generate a pattern failure whileinactivating the chemical amplification type resist. Further, breakingof the copper wiring occurs and the reliability of the semiconductordevice is deteriorated.

Accordingly, in the manufacturing method of a semiconductor device, atechnique for improving the reliability of the semiconductor device isrequired.

Other problems and new features will be apparent from the descriptionand the attached drawings of the specification.

According to one embodiment, a semiconductor substrate having a siliconnitride film on its rear surface is prepared, an interlayer insulatingfilm having a via hole on the main surface of the semiconductorsubstrate is formed, and a first photoresist film is formed selectivelywithin the via hole. Next, the wafer rear surface cleaning is performedto expose the surface of the silicon nitride film formed on the rearsurface of the semiconductor substrate, and thereafter, a secondphotoresist film made of chemical amplification type resist is formed onthe interlayer insulating film and the first photoresist film over themain surface of the semiconductor substrate. During these processes, thesemiconductor substrate is stored in an atmosphere with the ammonium ionconcentration of 1000 μg/m³ and less.

According to one embodiment, the reliability of a semiconductor devicecan be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart showing a part of the manufacturing process of asemiconductor device.

FIG. 2 is a flow chart showing a part of the manufacturing process of asemiconductor device following FIG. 1.

FIG. 3 is a cross-sectional view of an important portion showing themanufacturing process of a semiconductor device.

FIG. 4 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 3.

FIG. 5 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 4.

FIG. 6 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 5.

FIG. 7 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 6.

FIG. 8 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 7.

FIG. 9 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 8.

FIG. 10 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 9.

FIG. 11 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 10.

FIG. 12 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 11.

FIG. 13 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 12.

FIG. 14 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 13.

FIG. 15 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 14.

FIG. 16 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 15.

FIG. 17 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 16.

FIG. 18 is a cross-sectional view of the important portion showing themanufacturing process of a semiconductor device following FIG. 17.

FIG. 19 is a cross-sectional view showing the stored state of asemiconductor device in the manufacturing processes.

FIG. 20 is a cross-sectional view of an important portion showing themanufacturing process of a semiconductor device according to aconsidered example.

FIG. 21 is a view showing a relation between disconnection of wiring andammonium concentration.

FIG. 22 is a view showing the effect of the embodiment.

DETAILED DESCRIPTION

The following embodiments will be described, if necessary, for the sakeof convenience, divided into a plurality of sections or embodiments;except for the specified case, they are mutually related to each otherand one is a part or the whole of the other modified example, details,and additional description. In the following description, when referringto the number of elements (including the number of units, numeric value,amount, range), except for the case particularly specified and the caseof apparently restricted to a specified number in principle, they arenot restricted to the specified number but may be more or less than thespecified number. Further, in the following embodiments, it is needlessto say that the component elements (including the element step) are notalways required, except for the case particularly specified and the caseapparently required in principle. Similarly, in the followingembodiments, when referring to the shape and the positional relation ofthe component elements, they are to include their similar or likeshapes, except for the case particularly specified and the caseapparently different in principle. This is true to the above number andthe range.

Hereinafter, the embodiments will be described in detail with referenceto the drawings. In all the drawings for describing the embodiments, thesame reference numerals and symbols are attached to the materials havingthe same functions and their repeated description is omitted. Further,in the following embodiments, the description about the same or similarportion is not repeated except for the case especially required.

In the drawings used for the embodiments, even if in a cross-sectionalview, hatching may be sometimes omitted for the sake of simplicity. Onthe contrary, even if in a plan view, hatching may be performed for thesake of easy understanding of the view.

Embodiment

A semiconductor device according to an embodiment includes a pluralityof Meta Insulator Semiconductor Field Effect Transistors (MISFET). TheMISFETs include n-type MISFET Qn and p-type MISFET Qp. A semiconductordevice is formed in a rectangular chip region and a plurality of chipregions are arranged on the semiconductor wafer in a matrix shape. Aplurality of semiconductor devices are formed on one semiconductorwafer.

FIGS. 1 and 2 are flow views showing a part of the manufacturing processof a semiconductor device, and FIGS. 3 to 18 are cross-sectional viewsof an important portion showing the manufacturing process of asemiconductor device. FIG. 19 is a view showing the stored state amongthe manufacturing processes of a semiconductor device. FIG. 20 is across-sectional view of an important portion showing the manufacturingprocess of a semiconductor device in a considered example.

At first, as shown in FIG. 3, a semiconductor substrate 1S(semiconductor wafer WF), for example, made of silicon is prepared (StepS1 in FIG. 1). In the embodiment, although the description is made usingthe word “semiconductor substrate 1S”, it can be replaced with the word“semiconductor wafer WF”. The word of the semiconductor wafer WF issometimes used here. The semiconductor substrate 1S includes a mainsurface and a rear surface and the plan shape is circular (substantiallycircular). The main surface and the rear surface of the semiconductorsubstrate 1S are circular. As shown in FIG. 3, the semiconductorsubstrate 1S has an n-type MISFET Qn and a p-type MISFET Qp. Forexample, on the surface (main surface) of the p-type semiconductorsubstrate 1S, a p-type well layer PW that is a p-type semiconductorregion and an n-type well layer NW that is an n-type semiconductorregion are formed. Actually, within the p-type well layer PW, aplurality of n-type MISFETs Qn are formed and within the n-type welllayer NW, a plurality of p-type MISFETs Qp are formed. On the surface ofthe semiconductor substrate 1S, an element isolation film STI made of asilicon oxide film is formed to electrically isolate the n-type MISFETsQn and the p-type MISFETs Qp, or the n-type MISFET Qn and the p-typeMISFET Qp.

The n-type MISFET Qn includes a gate electrode GN formed on the mainsurface of the semiconductor substrate 1S through the gate insulatingfilm GI and a source region and drain region formed on the main surfaceof the semiconductor substrate 1S at the both ends of the gate electrodeGN. Each of the source region and the drain region includes an n-typelow concentration semiconductor layer NM and an n-type highconcentration semiconductor layer NH, and a silicide layer SIL is formedon the surface of the n-type high concentration semiconductor layer NH.The silicide layer SIL is formed also on the surface of the gateelectrode GN. A sidewall insulating film SW is formed on the sidewall ofthe gate electrode GN. The n-type low concentration semiconductor layerNM and the n-type high concentration semiconductor layer NH are in then-type semiconductor region and the n-type high concentrationsemiconductor layer NH is higher than the n-type low concentrationsemiconductor layer NM in the dopant concentration.

Further, the p-type MISFET Qp includes a gate electrode GP formed on themain surface of the semiconductor substrate 1S through the gateinsulating film GI and a source region and drain region formed on themain surface of the semiconductor substrate 1S at the both ends of thegate electrode GP. Each of the source region and the drain regionincludes a p-type low concentration semiconductor layer PM and a p-typehigh concentration semiconductor layer PH, and the silicide layer SIL isformed on the surface of the p-type high concentration semiconductorlayer PH. Further, the silicide layer SIL is formed on the surface ofthe gate electrode GP. Further, the sidewall insulating film SW isformed on the sidewall of the gate electrode GP. The p-type lowconcentration semiconductor layer PM and the p-type high concentrationsemiconductor layer PH are in the p-type semiconductor region and thep-type high concentration semiconductor layer PH is higher than thep-type low concentration semiconductor layer PM in the dopantconcentration.

The silicide layer SIL of the n-type MISFET Qn and the p-type MISFET Qpis made of cobalt silicide (CoSi), titanium silicide (TiSi), nickelsilicide (NiSi), or platinum containing nickel silicide (PtNiSi). Thesidewall insulating film SW is formed by a silicon nitride film, or astacked film including a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 4, an insulating film IF is formed over thesemiconductor substrate 1S (Step S2 in FIG. 1). The insulating film IFis formed to cover the n-type MISFET Qn and the p-type MISFET Qp.Specifically, it is formed to cover the silicide layers SIL of then-type MISFET Qn and the p-type MISFET Qp and the sidewall insulatingfilms SW. The insulating film IF is formed of a silicon nitride filmaccording to the LPCVD method with dichlorsilane (SiH₂Cl₂) and ammonia(NH₃) used as a source gas. By using the LPCVD method, a silicon nitridefilm can be a film of high covering property and high density. Further,as the insulating film IF, a silicon nitride film having tensile stressor compression stress can be also used. When the insulating film IF(silicon nitride film) is formed according to the LPCVD method, thesilicon nitride film is also formed on the rear surface of thesemiconductor substrate 1S.

As shown in FIG. 4, a contact interlayer insulating film CIL is formedon the insulating film IF on the side of the main surface of thesemiconductor substrate 1S (Step S3 in FIG. 1). The contact interlayerinsulating film CIL is formed of a silicon oxide film with a filmthickness more than the insulating film IF, according to thePlasma-Enhanced Chemical Vapor Deposition (PECVD) method (plasma CVDmethod). When using the plasma CVD method, since film formation isperformed with the rear surface of the semiconductor substrate 1Smounted on a stage, any contact interlayer insulating film CIL is notformed on the rear surface of the semiconductor substrate 1S but theinsulating film IF (silicon nitride film) is exposed on the rear surfaceof the semiconductor substrate 1S.

Next, as shown in FIG. 5, by using the photolithography technique andthe etching technique, a contact hole CNT is formed in the contactinterlayer insulating film CIL and the insulating film IF. This contacthole CNT is processed to penetrate the contact interlayer insulatingfilm CIL and the insulating film IF and arrive at the silicide layer SILformed on the surface of the source region and the drain region of then-type MISFET Qn and the p-type MISFET Qp. In the forming process of thecontact hole CNT, under the condition that the etching rate of thecontact interlayer insulating film CIL is higher, as for the insulatingfilm IF, the contact hole CNT is formed in the contact interlayerinsulating film CIL, and thereafter etching is performed under thecondition that the insulating film IF is etched. In short, theinsulating film IF works as an etching stopper. By making the insulatingfilm IF of a silicon nitride film formed according to the LPCVD method,an etching selection ratio to the contact interlayer insulating film CILcan be fully enhanced.

Next, as shown in FIG. 6, by embedding a metal film in the contact holeCNT formed in the contact interlayer insulating film CIL, a plug PLG1 isformed (Step S4 in FIG. 1). Specifically, a titanium/titanium nitridefilm as a barrier conductor film is formed on the contact interlayerinsulating film CIL with the contact hole CNT formed there, for example,according to the sputtering method. A tungsten film is formed on thetitanium/titanium nitride film. According to this, the titanium/titaniumnitride film is formed in the inner wall (sidewall and bottom) of thecontact hole CNT, and a tungsten film is formed on the titanium/titaniumnitride film to fill the contact hole CNT. Thereafter, only theunnecessary titanium/titanium nitride film and tungsten film formed onthe contact interlayer insulating film CIL is removed according to theChemical Mechanical Polishing (CMP) method. This can form the plug PLG1having the titanium/titanium nitride film and the tungsten film embeddedonly within the contact hole CNT. The titanium/titanium nitride film andthe tungsten film are not formed on the side of the rear surface of thesemiconductor substrate 1S.

As shown in FIG. 7, an interlayer insulating film IL1 is formed on thecontact interlayer insulating film CIL with the plug PLG1 formed there(Step S6 in FIG. 1). This interlayer insulating film IL1 is formed of,for example, a silicon oxide film, for example, according to the plasmaCVD method.

Next, before forming a wiring groove WD1 described later, scrub cleaning1 is performed on the main surface and the rear surface of thesemiconductor substrate 1S (Step S7 in FIG. 1). In the scrub cleaning 1,a rotary blush is operated while running pure water on the main surfaceand the rear surface of the semiconductor substrate 1S, hence to removethe fine particle (debris) attached to the main surface and the rearsurface.

Next, wafer rear surface cleaning 1 is performed on the rear surface ofthe semiconductor substrate 1S (Step S8 in FIG. 1). In the process ofthe wafer rear surface cleaning 1, Sulfuric acid Peroxide Mixture (SPM)cleaning and Fluoride acid Peroxide Mixture (FPM) cleaning are performedin this order. The wafer rear surface cleaning 1 is performed only onthe rear surface of the semiconductor substrate 1S, in a way of avoidingthe cleaning liquid from intruding into the main surface of thesemiconductor substrate 1S. The SPM cleaning is to remove an organicsubstance, using the mixed liquid of sulfuric acid and hydrogenperoxide. Further, the FPM cleaning is to remove metal contamination,using the mixed liquid of hydrofluoric acid and hydrogen peroxide. Here,instead of the SPM cleaning, Ammonia-Hydrogen Peroxide Mixture (APM)cleaning may be used, or instead of the FPM cleaning, DilutedHydrofluoric acid (DHF) cleaning may be used. The APM cleaning is toremove the organic substance using the mixed liquid of ammonia andhydrogen peroxide, and the DHF cleaning is to remove the metalcontamination using the mixed liquid of hydrofluoric acid and hydrogenperoxide. The FPM cleaning and the DHF cleaning are to remove the oxidefilm and can remove the metal attached to the oxide film together withthe oxide film. Alternatively, the metal intruded into the oxide filmcan be removed by being suspended. Here, the SPM cleaning and the FPMcleaning can avoid a so-called cross contamination.

As shown in FIG. 8, by using the photolithography technique and theetching technique, a wiring groove WD1 is formed in the interlayerinsulating film IL1 (Step S9 in FIG. 1). The wiring groove WD1 is formedso that it may penetrate the interlayer insulating film IL1 made of asilicon oxide film and arrive at the contact interlayer insulating filmCIL in its bottom surface. According to this, the surface (top surface)of the plug PLG1 is exposed in the bottom of the wiring groove WD1.

As shown in FIG. 10, a wiring L1 is formed within the wiring groove WD1(Step S10 in FIG. 1). At first, as shown in FIG. 9, a barrier conductorfilm (copper diffusion prevention film) BCF1 is formed on the interlayerinsulating film IL1 with the wiring groove WD1 formed there.Specifically, the barrier conductor film BCF1 is made of tantalum (Ta),titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), theirnitride, their silicide nitride, or their stacked film, for example,according to the sputtering method.

Continuously, for example, a seed film made of a thin copper film isformed on the barrier conductor film BCF1 formed inside the wiringgroove WD1 and on the interlayer insulating film IL1, according to thesputtering method. Then, a copper film CF1 is formed according to theelectrolytic plating method with the seed film used as an electrode. Thecopper film CF1 is formed in a stacked structure of the seed film and aplating film. The copper film CF1 is formed in a way of filling thewiring groove WD1. The copper film CF1 is formed of a film mainlyincluding, for example, copper. Specifically, it is formed of copper(Cu) or copper alloy (alloy of copper (Cu) and aluminum (Al), magnesium(Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium(Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd),silver (Ag), gold (Au), In (indium), lanthanide metal, or actinoid-basedmetal). In the case of the copper alloy, since the seed film is thealloy as mentioned above, the copper film CF1 becomes the copper alloy.The copper alloy described later is similarly made.

The barrier conductor film BCF1, the seed film, and the copper film CF1are not formed on the rear surface of the semiconductor substrate 1S.

Continuously, as shown in FIG. 10, the unnecessary barrier conductorfilm BCF1 and copper film CF1 formed on the interlayer insulating filmIL1 are removed according to the CMP method. According to this, thewiring L1 with the barrier conductor film BCF1 and the copper film CF1embedded into the wiring groove WD1 can be formed. The barrier conductorfilm BCF1 and the copper film CF1 between the wirings L1 are removed bythe CMP method and the mutually adjacent wirings L1 are electricallyisolated. In short, the main surface of the interlayer insulating filmIL1 positioned between the adjacent wirings L1 is exposed according tothe CMP method.

Continuously, the ammonia plasma treatment is performed on the surfaceof the interlayer insulating film IL1 with the wiring L1 formed there,to clean the surface of the wiring L1 and the surface of the interlayerinsulating film IL1.

Next, as shown in FIG. 11, a barrier insulating film BIF is formed onthe wiring L1 and the interlayer insulating film IL1 (Step S11 in FIG.1). The barrier insulating film BIF is made by a stacked film of an SiCNfilm SCN and an SiCO film SCO. The SiCN film SCN is formed on the wiringL1 and the interlayer insulating film IL1 according to the plasma CVDmethod with the tetramethyl silane gas and the ammonia gas used as thematerial gas. The SiCN film SCN is a copper diffusion prevention film ofthe copper film CF1 forming the wiring L1. According to the abovementioned ammonia plasma treatment, adhesion between the SiCN film SCNand the interlayer insulating film LI1 is improved and Time DependentDielectric Breakdown (TDDB) characteristic between the adjacent wiringsL1 is improved. In short, a leak current between the adjacent wirings L1can be reduced.

Further, the SiCO film SCO can be formed, for example, according to theplasma CVD method. The SiCO film SCO is provided in order to avoid thenitrogen or ammonium ion included in the SiCN film SCN from diffusing toa photoresist film PR3 described later. In short, the SiCO film SCO isto avoid the resist poisoning caused by the inactiveness of thephotoresist film PR3 in the photolithography process.

Any SiCN film SCN and SiO film SCO are not formed (deposited) on therear surface of the semiconductor substrate 1S.

Next, as shown in FIG. 12, an interlayer insulating film IL2 is formedon the barrier insulating film BIF and a damage protective film DP isformed on the interlayer insulating film IL2 (Step S12 in FIG. 1). Morespecifically, the interlayer insulating film IL2 is formed of, forexample, an SiOC film having holes of lower dielectric constant than thesilicon oxide film, an HSQ film having holes, or an MSQ film havingholes. The SiOC film having the holes can be formed, for example, usingthe plasma CVD method. The damage protective film DP is formed of, forexample, a tetra ethyl ortho silicate (TEOS) film, or a silicon oxidefilm, for example, according to the plasma CVD method. The damageprotective film DP is higher than the interlayer insulating film IL2 infilm density and mechanical intensity.

Next, before forming a photoresist film PR1 described later, scrubcleaning 2 is performed on the main surface and the rear surface of thesemiconductor substrate 1S (Step S13 in FIG. 2). The scrub cleaning 2 isperformed similarly to the above mentioned scrub cleaning 1.

This time, wafer rear surface cleaning 2 is performed on the rearsurface of the semiconductor substrate 1S (Step S14 in FIG. 2). Thewafer rear surface cleaning 2 is performed similarly to the wafer rearsurface cleaning 1.

As shown in FIG. 13, a photoresist film PR1 made of a chemicalamplification type resist is formed on the damage protective film DP(Step S15 in FIG. 2). The chemical amplification type resist is appliedto the damage protective film DP and by performing the exposure anddevelopment treatment, the chemical amplification type resist ispatterned to form the photoresist film PR1. The patterning is performedto bore each region to form a via hole VH. Thereafter, with a mask ofthe patterned photoresist film PR1, the damage protective film DP andthe interlayer insulating film IL2 are etched. Thus, the via holes VH toexpose the SiCO film SCO are formed by penetrating the damage protectivefilm DP and the interlayer insulating film IL2 (Step S16 in FIG. 2).This SiCO film SCO works as the etching stopper in the etching.

Next, as shown in FIG. 14, a via-fill PR2 (via-fill film PR2) is formedonly within the via hole VH (Step S17 in FIG. 2). The via-fill PR2 is anorganic film made of the substantially same material as that of thephotoresist films PR1 and PR3 and can be removed according to the plasmaashing treatment. At first, the via-fill PR2 is formed over thesemiconductor substrate 1S to completely fill the via hole VH, and thevia-fill PR2 is formed within the via hole VH and on the damageprotective film DP. Next, the plasma ashing treatment is performed onthe via-fill PR2, using a gas such as ozone (O₃) or oxygen (O₂), and thevia-fill PR2 for the same film thickness as the via-fill PR2 on thedamage protective film DP is selectively removed through the plasmaashing treatment. Here, the via-fill PR2 on the damage protective filmDP is completely removed but the plasma ashing treatment does not affectthe via-fill PR2 within the via hole VH and it is important toselectively leave the via-fill PR2 within the via hole VH.

In the above mentioned forming process of the photoresist film PR1 andthe via-fill PR2, the photoresist film PR1 and the via-fill PR2 are notformed on the rear surface of the semiconductor substrate 1S. Since theplasma asking treatment is performed in a state where the rear surfaceof the semiconductor substrate 1S is exposed, the surface of the siliconnitride film formed on the rear surface of the semiconductor substrate1S is oxidized, to form a natural oxide.

Before a photoresist film PR3 described later is formed, scrub cleaning3 is performed on the main surface and the rear surface of thesemiconductor substrate 1S (Step S18 in FIG. 2). The scrub cleaning 3 isperformed similarly to the above mentioned scrub cleaning 1.

Next, wafer rear surface cleaning 3 is performed on the rear surface ofthe semiconductor substrate 1S (Step S19 in FIG. 2). The wafer rearsurface cleaning 3 is performed similarly to the wafer rear surfacecleaning 1. In the SPM cleaning process of the wafer rear surfacecleaning 3, the surface of the silicon nitride film formed on the rearsurface of the semiconductor substrate 1S is oxidized to form a naturaloxide, and thereafter, when the FPM cleaning is performed, the naturaloxide (oxide film) on the surface of the silicon nitride film is removedand the surface of the silicon nitride film gets into an exposed state.

Next, as shown in FIG. 15, a photoresist film PR3 as a mask for forminga wiring groove WD2 described later is formed on the damage protectivefilm DP (Step S20 in FIG. 2). A positive chemical amplification typeresist is applied to the via-fill PR2 within the via hole VH and on thedamage protective film DP (application process), and a heating treatmentbefore exposure is performed there to vaporize the organic solvent(heating process before exposure). Then, the exposure process isperformed. Specifically, the region to form the wiring groove WD2described later is irradiated with ultraviolet ray by an excimer laser.Then, when a heating treatment after exposure is performed on thechemical amplification type resist, deprotection reaction proceeds inthe irradiated region of ultraviolet ray (exposure region) and into amolecular structure dissolvable into alkali developing solution (heatingprocess after exposure). The chemical amplification type resist in theirradiated region is removed through the developing processing, hence toform the photoresist film PR3 having each aperture corresponding to eachwiring groove WD2 described later (development process). Here, thewiring groove WD2 is formed on the via hole VH. In plan view, the viahole VH has a circular, the width of the wiring groove WD2 is thediameter of the via hole VH and more, and the length of the wiringgroove WD2 is more (longer) than the diameter of the via hole VH.

Then, as shown in FIG. 16, using the etching technique, the wiringgroove WD2 is formed on the interlayer insulating film IL2 and thedamage protective film DP (Step S21 in FIG. 2). Specifically, thepatterned photoresist film PR3 shown in FIG. 15 is used as a mask toperform the anisotropy dry etching and the respective wiring grooves WD2are formed on the damage protective film DP and the interlayerinsulating film IL2. Before application of the chemical amplificationtype resist, an anti-reflection film made of an organic film such asBottom Antireflective Coating (BARC) may be provided on the damageprotective film DP.

After forming the wiring groove WD2, the via-fills PR2 and PR3 areremoved by the plasma ashing treatment. When provided with theanti-reflection film, the anti-reflection film is also removed by theplasma ashing treatment. Then, the barrier insulating film BIF exposedto the via hole VH is removed by the dry etching technique (Step S22 inFIG. 2), to expose the top surface of the wiring L1. The damageprotective film DP as an insulating film having a higher density thanthe interlayer insulating film IL2 is provided on the interlayerinsulating film IL2, which can avoid or decrease the following problemsin the dry etching process. Specifically, when the damage protectivefilm DP is not formed, there occur the following problems: since the dryetching treatment is performed on the surface of the interlayerinsulating film IL2 having a low density, the surface of the interlayerinsulating film IL2 gets rough, and since the surface is etched, thefilm thickness of the interlayer insulating film IL2 is decreased.

As shown in FIG. 17, a barrier conductor film (copper diffusionprotective film) BCF1 is formed inside the wiring groove WD2 and the viahole VH and on the damage protective film DP. Specifically, the barrierconductor film BCF1 is made of tantalum (Ta), titanium (Ti), ruthenium(Ru), tungsten (W), manganese (Mn), their nitride, their silicidenitride, or their stacked film, for example, according to the sputteringmethod. Continuously, for example, a seed film made of a thin copperfilm is formed on the barrier conductor film BCF2 formed inside thewiring groove WD2 and on the damage protective film DP, according to thesputtering method. Then, a copper film CF2 is formed with this seed filmused as the electrode according to the electrolytic plating method. Thecopper film CF2 is formed in a stacked structure including the seed filmand the plating film, to fill the wiring groove WD2. This copper filmCF2 is formed of, for example, a film mainly including copper.Specifically, it is formed of copper (Cu) or copper alloy (alloy ofcopper (Cu) and aluminum (Al), magnesium (Mg), titanium (Ti), manganese(Mn), iron (Fe), zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum(Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), In(indium), lanthanide metal, or actinoid-based metal).

As shown in FIG. 18, the unnecessary barrier conductor film BCF2 andcopper film CF2 formed on the damage protective film DP are removed bythe CMP method. Here, the damage protective film DP is also removed bythe CMP method, a wiring L2 formed by embedding the barrier conductorfilm BCF2 and the copper film CF2 into the wiring groove WD2 and a plugelectrode PLG2 formed by embedding the barrier conductor film BCF2 andthe copper film CF2 into the via hole VH can be formed (Step S23 in FIG.2). In other words, only the interlayer insulating film IL2 having a lowdielectric constant is left between the wirings L2 and the parasiticcapacitance between the adjacent wirings L2 can be reduced. By havingprovided with the damage protective film DP, the CMP polishing damage onthe surface of the interlayer insulating film IL2 between the wirings L2can be avoided (reduced) and a leak current between the wirings L2 canbe reduced when removing the copper film CF2 and the barrier conductorfilm BCF2 according to the CMP polishing.

By repetition of the processes from Step S11 in FIG. 1 to Step S23 inFIG. 2, a multi layer wiring can be formed above the wiring L2.

During a period from the completion of the above mentioned wafer rearsurface cleaning 3 (especially, the FPM cleaning) in Step S19 to thephotoresist film PR3 formation process in Step S20, the semiconductorsubstrate 1S (semiconductor wafer WF) is accommodated in the sealed typetransfer container FP including purge holes PG1 and PG2 shown in FIG.19. The sealed type transfer container FP is the container capable ofaccommodating, for example, 24 sheets of semiconductor wafers having adiameter of 300 mm with a door (open-and-close window). In the closedstate of the door, airtightness is kept inside the sealed type transfercontainer FP.

In the embodiment, it is important that the sealed type transfercontainer FP is purged with a nitrogen (N₂) gas, in order to keep theinside of the sealed type transfer container FP at a desired atmosphere.In other words, a nitrogen (N₂) gas is inserted into the sealed typetransfer container FP through the purge hole PG1 and exhausted from thepurge hole PG2, hence to keep (control) the concentration of ammoniumion (NH₄ ⁺) inside the sealed type transfer container FP at 1000 μg/m³and less. As mentioned above, the semiconductor substrate 1S is carriedamong the processes, being accommodated into the sealed type transfercontainer FP; unless otherwise specified, the sealed type transfercontainer FP is not purged with the nitrogen (N₂) gas.

This time, a problem in the case of no control (no purge with nitrogen)performed on the concentration of the ammonium ion (NH₄ ⁺) within thesealed type transfer container FP will be described.

As mentioned above, at a time of finishing the wafer rear surfacecleaning 3 (especially, the FPM cleaning) in Step S19, the natural oxide(oxide film) on the surface of the silicon nitride film formed on therear surface of the semiconductor substrate 1S is removed and thesurface of the silicon nitride film is exposed. In other words, sincethe ammonium ion (NH₄ ⁺) is constantly exhausted from the siliconnitride film, the concentration of the ammonium ion (NH₄ ⁺) within thesealed type transfer container FP rises. The ammonium ion (NH₄ ⁺)intrudes into the via-fill PR2 formed on the main surface of thesemiconductor substrate 1S, to form amine. In short, the via-fill PR2formed in the via hole VH in FIG. 14 contains a large amount of amine.

As mentioned above using FIG. 15, although a positive chemicalamplification type resist is formed on the via-fill PR2 formed withinthe via hole VH, to form the photoresist film PR3 having openingportions corresponding to the respective wiring grooves WD2, the amineincluded in the via-fill PR2 is diffused and intruded into the chemicalamplification type resist, hence to disturb the deprotection reaction inthe exposure region and after the development process, a part of thechemical amplification type resist is left without being removed,although it is in the exposure region. Accordingly, when performing theanisotropy dry etching on the damage protective film DP and theinterlayer insulating film IL2 with the photoresist film PR3 used as themask, there is a problem that the original wiring groove WD2 is notformed, as shown in FIG. 20. Further, after removing the via-fill PR2and the photoresist film PR3 by the plasma ashing treatment, therearises a problem that breaking occurs in the wiring L2 when forming thewiring L2 and the plug electrode PLG2 within the wiring groove WD2 andthe via hole VH. In other words, because of the ammonium ion included inthe silicon nitride film formed on the rear surface of the semiconductorsubstrate 1S, resist poisoning occurs in the chemical amplification typeresist and the breaking of the wiring L2 occurs. The left portion inFIG. 20 indicates the case of the photoresist film PR3 normally formedand the right portion indicates the case of the photoresist film PR3 notnormally formed with occurrence of a bad resolution.

The inventor et al. come to arrive at the following view as the resultof consideration to a relation between the ammonium ion (NH₄ ⁺) withinthe sealed type transfer container FP and the breaking.

FIG. 21 is a view showing a relation between the breaking of the wiringL2 and the ammonium ion (NH₄ ⁺) concentration within the sealed typetransfer container FP. The case of storing twelve semiconductor wafersWF within the sealed type transfer container FP is compared with thecase of storing twenty four wafers. The semiconductor wafer WF is in astate of having been subjected to the above mentioned wafer rear surfacecleaning 3 (especially, the FPM cleaning) in Step S19, before thephotoresist film PR3 forming process in Step S20, and the sealed typetransfer container FP is hermetically closed without being purged withthe nitrogen (N₂).

In the case of storing the twelve semiconductor wafers WF within thesealed type transfer container FP, the ammonium ion (NH₄ ⁺)concentration rises from the start of the store, arriving at the maximumof about 900 μg/m³ on the fourth day, then, the ammonium ion is absorbedby the via-fill PR2 on the main surface of the semiconductor substrate1S, and the concentration is reduced. No breaking is found in the twelvesemiconductor wafers WF.

On the other hand, in the case of storing the twenty four semiconductorwafers WF within the sealed type transfer container FP, the ammonium ion(NH₄ ⁺) concentration rises continuously from the start of the store andarrives at 2000 μg/m³ and more on the second day from the start.Breaking is found in the semiconductor wafers WF stored for the two daysand more from the start. In FIG. 21, breaking is confirmed in thehatched region exceeding the ammonium ion (NH₄ ⁺) concentration of 1000μ/m³.

From the above result, in order to avoid the breaking, it is importantthat the ammonium ion (NH₄ ⁺) concentration within the sealed typetransfer container FP should be kept (controlled) at 1000 μg/m³ andless.

In the embodiment, it is important that after having been subjected tothe wafer rear surface cleaning 3 (especially, the FPM cleaning) in StepS19, the semiconductor substrate 1S (semiconductor wafer WF) before thephotoresist film PR3 forming process in Step S20 should be kept in anatmosphere with the ammonium ion (NH₄ ⁺) concentration of 1000 μg/m³ andless. The sealed type transfer container FP may be purged with aninactive gas such as argon (Ar) instead of nitrogen (N₂), hence tocontrol the ammonium ion concentration within the sealed type transfercontainer FP.

According to the embodiment, the following effects can be obtained.

After performing the wafer rear surface cleaning 3 on the rear surfaceof the semiconductor substrate 1S, the semiconductor substrate 1S isstored within the sealed type transfer container FP and the ammonium ionconcentration within the sealed type transfer container FP is controlledat 1000 μg/m³ and less. According to this, it is possible to avoid thebreaking of the wiring L2 generated by the resist poisoning of thephotoresist film PR3 made of a positive chemical amplification typeresist and improve the reliability of the semiconductor device.

Since the FPM cleaning is performed in the wafer rear surface cleaning3, it is possible to avoid (reduce) the cross contamination in themanufacturing process of a semiconductor device and improve themanufacturing yield of the semiconductor device.

By controlling the ammonium ion (NH₄ ⁺) concentration within the sealedtype transfer container FP, it is possible to avoid a failure of thein-process product caused by a trouble of a device. Even when thesemiconductor substrate 1S having been subjected to the wafer rearsurface cleaning 3 is stored within the sealed type transfer containerFP for a long time, the ammonium ion (NH₄ ⁺) concentration does notexcessively rise; there is no need to worry about the breaking of thewiring L2 caused by the resist poisoning.

As described by using FIG. 13, the photoresist film PR1 made of thechemical amplification type resist is used in forming the via hole VH,the wafer rear surface cleaning 2 is performed also before forming thephotoresist film PR1, and the surface of the silicon nitride film formedon the rear surface of the semiconductor substrate 1S is exposed. Duringthe period from the wafer rear surface cleaning 2 to the photoresistfilm PR1 formulation, the semiconductor substrate 1S is stored withinthe sealed type transfer container FP. In the patterning of thephotoresist film PR1, however, the resist poisoning phenomenon is notfound.

This can derive the assumption that the resist poisoning occurs in thephotoresist film PR3 effected by the via-fill PR2 embedded into the viahole VH, when forming the wiring groove WD2. In other words, theammonium ion (NH₄ ⁺) released from the rear surface of the semiconductorsubstrate 1S intrudes into the via-fill PR2 made of an organic film anda large amount of amine is generated; as the result, the resistpoisoning occurs in the photoresist film PR3. The embodiment iseffective especially in the case of the via-fill PR2 (organic film) indirect contact with the photoresist film PR3 existing in the lowerlayer.

Modified Example 1

In a modified example 1, a scrub cleaning treatment while running purewater is performed on the rear surface of the semiconductor substrateis, continued to the wafer rear surface cleaning 3 in Step S19 in FIG.2. In short, after sequentially performing the SPM cleaning and the FPMcleaning as the wafer rear surface cleaning 3 in Step 19, the pure waterscrub cleaning is additionally performed on the rear surface of thesemiconductor substrate 1S, and thereafter, the semiconductor substrate1S is stored in the sealed type transfer container FP. Then, during thephotoresist film PR3 forming process in Step S20, it is stored in thesealed type transfer container FP, with no need to manage the ammoniumion (NH₄ ⁺) concentration within the sealed type transfer container FP.In short, there is no need to purge the sealed type transfer containerFP with the nitrogen (N₂).

As mentioned above, after the FPM cleaning of the wafer rear surfacecleaning 3, the silicon nitride film on the rear surface of thesemiconductor substrate 1S is exposed; however, by performing the purewater scrub cleaning, a thin silicon oxide film can be formed on thesurface of the silicon nitride film, hence to avoid (reduce) theammonium ion from exhausting from the silicon nitride film. Therefore,even when the semiconductor substrate 1S is stored in the sealed typetransfer container FP without purge with the nitrogen (N₂), the ammoniumion (NH₄ ⁺) concentration within the sealed type transfer container FPcan be kept at 1000 μg/m³ and less, hence to avoid the breaking of thewiring L2.

Needless to say, the semiconductor substrate 1S having been subjected tothe pure ware scrub cleaning may be stored in the sealed type transfercontainer FP purged with the nitrogen (N₂). When carbon dioxide (CO₂)mixed pure water, ozone (O₃) water, or hydrogen peroxide (H₂O₂) is used,instead of pure water, the same effect can be obtained.

Modified Example 2

In a modified example 2, the wafer rear surface cleaning 3 in Step S19in FIG. 2 includes only the SPM cleaning and does not include the FPMcleaning. In short, after performing the SPM cleaning as the wafer rearsurface cleaning 3 in Step S19, the semiconductor substrate 1S is storedin the sealed type transfer container FP. Until the photoresist film PR3forming process in Step S20, it is stored in the sealed type transfercontainer FP. Also in this case, there is no need to control theammonium ion (NH₄ ⁺) concentration within the sealed type transfercontainer FP. In other words, the sealed type transfer container FP doesnot have to be purged with the nitrogen (N₂).

Since the SPM cleaning is included in the wafer rear surface cleaning 3,the surface of the silicon nitride film on the rear surface of thesemiconductor substrate 1S is in a state of being covered with a thinsilicon oxide film, which can avoid (suppress) the ammonium ion fromexhausting from the silicon nitride film. Even when the semiconductorsubstrate 1S is stored in the sealed type transfer container FP withoutpurge with the nitrogen (N₂), the ammonium ion (NH₄ ⁺) concentration canbe kept at 1000 μg/m³ and less within the sealed type transfer containerFP, which can avoid the breaking of the wiring L2.

Needless to say, the semiconductor substrate 1S just after the SPMcleaning may be stored in the sealed type transfer container FP purgedwith the nitrogen (N₂).

FIG. 22 is a view showing the effect of the embodiment (including themodified examples 1 and 2). In the horizontal axis in FIG. 22, (A) showsthe example of storing the semiconductor substrate 1S having beensubjected to the wafer rear surface cleaning 3, in the sealed typetransfer container FP purged with the nitrogen (N₂), (B) shows theexample of storing the semiconductor substrate 1S having been subjectedto the pure water scrub cleaning after the wafer rear surface cleaning3, in the sealed type transfer container FP without purge of thenitrogen (N₂), (C) shows the example of storing the semiconductorsubstrate 1S having been subjected to only the SPM cleaning of the waferrear surface cleaning 3, in the sealed type transfer container FPwithout purge of the nitrogen (N₂), and (D) shows the example(conventional example) of storing the semiconductor substrate 1S havingbeen subjected to the wafer rear surface cleaning 3, in the sealed typetransfer container FP without purge of the nitrogen (N₂). With thestored period defined as 4.5 days, it shows the ammonium ion (NH₄ ⁺)concentration in the sealed type transfer container FP, in each example.In the examples of (A), (B) and (C), the ammonium ion (NH₄ ⁺)concentration is less than 1000 μg/m³, with no occurrence of thebreaking of the wiring L2, but in the example of (D), the breakingoccurs.

According to the embodiments (including the modified examples 1 and 2),it is possible to avoid the breaking of the wiring L2, hence to improvethe reliability of the semiconductor device.

As set forth hereinabove, although the invention made by the inventor etal. has been described in detail based on the embodiments, it isneedless to say that the invention is not restricted to this embodimentsbut various modifications are possible without departing from the spiritof the invention.

The above embodiments have been described using the example of forming asilicon nitride film on the rear surface of the semiconductor substrate1S at a time of forming the insulating film IF working as an etchingstopper; however, since a silicon nitride film forming the sidewallinsulating film SW is also formed by the LPCVD method, a silicon nitridefilm is simultaneously formed on the main surface and the rear surfaceof the semiconductor substrate 1S. Therefore, the silicon nitride filmfor the sidewall insulating film SW is sometimes formed also on the rearsurface of the semiconductor substrate 1S and the breaking of the wiringL2 can be avoided similarly to the embodiments.

What is claimed is:
 1. A manufacturing method of a semiconductor devicecomprising steps of: (a) preparing a semiconductor substrate including amain surface and a rear surface, provided with a first silicon nitridefilm over the rear surface; (b) forming a first insulating filmincluding a first opening portion over the main surface of thesemiconductor substrate; (c) selectively forming a via-fill film made ofan organic film within the first opening portion; (d) after the step(c), cleaning the rear surface of the semiconductor substrate to removea natural oxide film on the first silicon nitride film so as to exposethe first silicon nitride film; (d1) after the step (d), storing thesemiconductor substrate in a sealed type transfer container in which thefirst silicon nitride film releases ammonium ions in the sealed typetransfer container; (d2) after the step (d1), purging, through a purgehole in the sealed type transfer container, the ammonium ions with aninactive gas to control ammonium ion concentration in the sealed typetransfer container; and (e) after the step (d2), forming a photoresistfilm made of chemical amplification type resist over the firstinsulating film and the via-fill film, wherein the photoresist filmincludes a second opening portion larger than the first opening portion,overlapping with the first opening portion.
 2. The method according toclaim 1, wherein the ammonium ion concentration in the sealed typetransfer container is controlled by purging the inactive gas to be 1000μg/m3 and less.
 3. The method according to claim 1, wherein in the step(d), a mixed liquid of hydrofluoric acid and hydrogen peroxide is usedto remove the oxide film covering the first silicon nitride film formedover the rear surface of the semiconductor substrate so as to expose thefirst silicon nitride film.
 4. The method according to claim 1, furthercomprising steps of: after the step (e), (f) forming a third openingportion corresponding to the second opening portion in the firstinsulating film, by etching the first insulating film; (g) forming ametal film on the first insulating film to fill the first openingportion and the third opening portion; and (h) after the step (g),forming a wiring in the third opening portion and a plug electrode inthe first opening portion, by performing a Chemical Mechanical Polishing(CMP) treatment on the metal film to remove a portion of the metal filmaround the third opening portion and expose the first insulating film.5. The method according to claim 4, wherein the metal film is made of acopper film.
 6. The method according to claim 1, wherein the step (a)further includes sub-steps of: (a1) forming a Metal InsulatorSemiconductor Field Effect Transistor (MISFET) including a gateelectrode, a source region, and a drain region, over the main surface ofthe semiconductor substrate; and (a2) after the step (a1), forming asecond silicon nitride film over the main surface of the semiconductorsubstrate to cover the MISFET by a Low Pressure Chemical VaporDeposition (LPCVD) method, and simultaneously, forming the first siliconnitride film over the rear surface of the semiconductor substrate. 7.The method according to claim 1, wherein the step (e) further includessub-steps of: (e1) applying the chemical amplification type resist tocover the first insulating film and the via-fill film; (e2) irradiatingthe chemical amplification type resist with ultraviolet ray; (e3) afterthe step (e2), heating the chemical amplification type resist; and (e4)after the step (e3), developing the chemical amplification type resist.8. The method according to claim 1, wherein the inactive gas is made ofnitrogen or argon.